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ADG465
When a negative overvoltage is applied to the channel protector
circuit, the PMOS transistor enters a saturated mode of operation
as the drain voltage exceeds V SS – V TP . See Figure 9 below. As in
the case of the positive overvoltage, the other MOS devices are
nonsaturated.
TRENCH ISOLATION
The MOS devices that make up the channel protector are
isolated from each other by an oxide layer (trench) (see Figure
11). When the NMOS and PMOS devices are not electrically
isolated from each other, there exists the possibility of “latchup”
NEGATIVE
OVERVOLTAGE
(–20V)
V SS – V TP *
(–13V)
caused by parasitic junctions between CMOS transistors. Latchup
is caused when P-N junctions that are normally reverse biased,
become forward biased, causing large currents to flow. This can
NEGATIVE
NMOS
PMOS
NMOS
be destructive.
OVERVOLTAGE
(–20V)
CMOS devices are normally isolated from each other by
NON- SATURATED
SATURATED
V DD (+15V) V SS (–15V)
*V TP = PMOS THRESHOLD VOLTAGE (+2V)
NON-
SATURATED
V DD (+15V)
Junction Isolation . In Junction Isolation, the N and P wells of the
CMOS transistors form a diode that is reverse biased under
normal operation. However, during overvoltage conditions, this
diode becomes forward biased. A Silicon-Controlled Rectifier
(SCR) type circuit is formed by the two transistors, causing a
Figure 9. Negative Overvoltage on the Channel Protector
The channel protector is also functional when the supply rails
are down (e.g., power failure) or momentarily unconnected
significant amplification of the current that, in turn, leads to
latchup. With Trench Isolation, this diode is removed; the result
is a latchup-proof circuit.
(e.g., rack system). This is where the channel protector has an
advantage over more conventional protection methods such as
V S
V G
V D
V S
V G
V D
diode clamping (see Applications Information). When V DD and
V SS equal 0 V, all transistors are off and the current is limited to
microampere levels (see Figure 10).
T
R
E
P +
P-CHANNEL
P +
T
R
E
N +
N-CHANNEL
N +
T
R
E
N
N
N
(0V)
C
H
N –
C
H
P –
C
H
BURIED OXIDE LAYER
POSITIVE OR
NEGATIVE
NMOS
PMOS
NMOS
SUBSTRATE (BACKGATE)
OVERVOLTAGE
OFF
V DD (0V)
OFF
V SS (0V)
OFF
V DD (0V)
Figure 11. Trench Isolation
Figure 10. Channel Protector Supplies Equal to Zero Volts
–6 –
REV. A
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